april 2012 FDMA8884 n-channel power trench ? mosfet ?2012 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMA8884 rev.c3 FDMA8884 single n-channel power trench ? mosfet 30 v, 6.5 a, 23 m features ? max r ds(on) = 23 m at v gs = 10 v, i d = 6.5 a ? max r ds(on) = 30 m at v gs = 4.5 v, i d = 6.0 a ? high performance trench technology for extremely low r ds(on) ? fast switching speed ? rohs compliant general description this n-channel mosfet is produced using fairchild semiconductor?s advanced power trench ? process that has been optimized for r ds(on) switching performance. application ? primary switch d d s g d d pin 1 drain source microfet 2x2 (bottom view) bottom drain contact d d d d s g mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 30 v v gs gate to source voltage (note 3) 20 v i d drain current -continuous (package limited) t c = 25 c 8.0 a 6.5 -continuous t a = 25 c (note 1a) -pulsed 25 p d power dissipation (note 1a) 1.9 w power dissipation (note 1b) 0.7 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 65 c/w r ja thermal resistance, junction to ambient (note 1b) 180 device marking device package reel size tape width quantity 884 FDMA8884 microfet 2x2 7 ?? 12 mm 3000 units
FDMA8884 n-channel power trench ? mosfet ?2012 fairchild semiconductor corporation 2 www.fairchildsemi.com FDMA8884 rev.c3 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 15 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a i gss gate to source leakage current, forward v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a1.21.83.0v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 6.5 a 19 23 m v gs = 4.5 v, i d = 6.0 a 25 30 v gs = 10 v, i d = 6.5 a, t j = 125 c 25 30 g fs forward transconductance v dd = 5 v, i d = 6.5 a 26 s c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1 mhz 339 450 pf c oss output capacitance 132 175 pf c rss reverse transfer capacitance 18 28 pf r g gate resistance 1.1 t d(on) turn-on delay time v dd = 15 v, i d = 6.5 a, v gs = 10 v, r gen = 6 510ns t r rise time 110ns t d(off) turn-off delay time 11 20 ns t f fall time 110ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 15 v i d = 6.5 a 5.4 7.5 nc total gate charge v gs = 0 v to 4.5 v 2.7 3.7 nc q gs total gate charge 1.0 nc q gd gate to drain ?miller? charge 0.9 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 6.5 a (note 2) 0.86 1.2 v t rr reverse recovery time i f = 6.5 a, di/dt = 100 a/ s 16 28 ns q rr reverse recovery charge 4 10 nc notes: 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0 %. 3. as an n-ch device, the negative vgs rating is for low duty cycle pulse occurrence only. no continuous rating is implied. a. 65 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 180 c/w when mounted on a minimum pad of 2 oz copper.
FDMA8884 n-channel power trench ? mosfet ?2012 fairchild semiconductor corporation 3 www.fairchildsemi.com FDMA8884 rev.c3 typical characteristics t j = 25 c unless otherwise noted figure 1. 0 0.4 0.8 1.2 1.6 2.0 0 5 10 15 20 25 v gs = 6 v v gs = 4.5 v v ds , drain to source voltage (v) i d , drain current (a) v gs = 4 v v gs = 3.5 v v gs = 10 v pulse duration = 80 p s duty cycle = 0.5% max on region characteristics figure 2. 0 5 10 15 20 25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v gs = 10 v v gs = 3.5 v v gs = 4 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 4.5 v v gs = 6 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 i d = 6.5 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 20 40 60 80 pulse duration = 80 p s duty cycle = 0.5% max t j = 125 o c t j = 25 o c i d = 6.5 a r ds(on) , drain to source on-resistance ( m : ) v gs , gate to source voltage (v) o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 12345 0 5 10 15 20 25 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.20.40.60.81.01.2 0.01 0.1 1 10 30 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMA8884 n-channel power trench ? mosfet ?2012 fairchild semiconductor corporation 4 www.fairchildsemi.com FDMA8884 rev.c3 figure 7. 0123456 0 2 4 6 8 10 i d = 6.5 a v dd = 20 v v dd = 15 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 10 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 500 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 100 0.01 0.1 1 10 30 100 p s 1 ms 1 s 10 ms dc 10 s 100 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 180 o c/w t a = 25 o c forward bias safe operating area figure 10. 10 -4 10 -3 10 -2 10 -1 110 100 10 3 0.5 1 10 100 200 single pulse r t ja = 180 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation figure 11. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.005 0.01 0.1 1 single pulse r t ja = 180 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to-ambient transient thermal response curve figure 12. typical characteristics t j = 25 c unless otherwise noted
FDMA8884 n-channel power trench ? mosfet ?2012 fairchild semiconductor corporation 5 www.fairchildsemi.com FDMA8884 rev.c3 dimensional outline and pad layout b. dimensions are in millimeters. c. dimensions and tolerances per a. does not fully conform to jedec registration asme y14.5m, 1994 0.10 cab 0.05 c recommended land pattern opt 1 0.10 c 0.08 c c 2.000 2.000 0.05 0.00 0.10 c 2x 2x 0.8 max seating plane 0.10 c (0.20) 0.33 0.20 1 3 4 6 4 6 3 1 pin #1 ident 0.65 1.30 1.35 (0.47) 1.05 0.40 typ 0.65 typ 0.25~0.35 1.000 0.800 2.30 1.00 mo-229 dated aug/2003 (0.56) (0.30) 0.66 recommended land pattern opt 2 4 6 3 1 1.35 (0.47) 1.05 0.40 typ 0.65 typ 2.30 1.00 0.66 no drain or gate traces allowed in this area pin#1 location 1.05 0.95 d. drawing filename: mkt-mlp06lrev2.
FDMA8884 n-channel power trench ? mosfet ?2012 fairchild semiconductor corporation 6 www.fairchildsemi.com FDMA8884 rev.c3 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions , specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably ex pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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